1. Field of the Invention
The invention relates in general to a method for manufacturing dynamic random access memory (DRAM). More particularly, the invention relates to the manufacturing of a DRAM capacitor that has a larger electrode surface area for increasing the memory storage capacity of a DRAM.
2. Description of the Related Art
As microprocessors become more powerful and the amount of software data that needs to be processed becomes very large, the amount of memory necessary for storing data becomes great. FIG. 1 is a circuit diagram showing a DRAM memory unit. A DRAM memory unit comprises a pass transistor 10 and a storage capacitor 11. The source terminal of the pass transistor 10 is connected to a bit line 12, the gate terminal is connected to a word line 13, and the drain terminal is connected to the storage electrode, known also as the lower electrode 14, of a storage capacitor 11. The plate electrode 15, also known as an upper electrode or a cell plate, is connected to a fixed voltage source. Between the storage electrode 14 and the plate electrode is a dielectric thin film 16.
When a small charge storage capacity is needed in a DRAM capacitor, a conventional two-dimensional or a planar type of capacitor can be fabricated in the integrated circuit. However, a planar type capacitor occupies a rather large surface area on the semiconductor substrate surface, hence is not suitable for high levels of integration. Therefore, three-dimensional capacitors, for example, the so-called stacked type or trench type capacitors, are used for increasing the level of integration of DRAMs. Nowadays, even the simple three-dimensional capacitor design is insufficient to provide the necessary capacitance. Consequently, methods of producing DRAM capacitors that can increase the surface area of the lower electrode within a given substrate area are still being developed.
FIG. 2 is a cross-sectional view of a conventional stacked type DRAM capacitor structure. First, a semiconductor substrate 20 having a metallic oxide semiconductor (MOS) transistor 22 already formed thereon is provided. The MOS transistor includes a gate terminal 23, source/drain region 24 and spacers 25. On top of the substrate 20, there is a field oxide layer 26 and a conductive layer 27. Next, insulating material is deposited over the substrate to form an insulating layer 28, and then the insulating layer 28 is etched to form contact windows at designated locations above the source/drain regions 24. Thereafter, a lower electrode 29, a dielectric layer 210 and an upper electrode 211 are sequentially formed above the contact windows to form a stacked capacitor structure 212. The dielectric layer 210 can be a silicon nitride/silicon dioxide (NO) composite layer or a silicon dioxide/silicon nitride/silicon dioxide (ONO) composite layer. The lower electrode 29 and the upper electrode 211 can be polysilicon layers. Furthermore, the lower electrode 29 can have an undulating and non-planar profile. Finally, subsequent processing operations such as the formation of a metallic contact and protective insulating layer are performed to complete the DRAM capacitor structure.
FIG. 3A-3F are cross-sectional views showing the progression of manufacturing steps in the fabrication of a cylinder DRAM capacitor according to a conventional method. First, referring to FIG. 3A, a first oxide layer 304 is formed on a MOS device 300, with a source/drain region 301, a field oxide layer 302 and gate electrode 303 provided on the MOS device 300. A thin silicon nitride layer 305 is formed on a surface of the first oxide layer 304 to be an etching stop layer in follow-up steps.
Referring to FIG. 3B, a photolithography step is promoted to pattern the silicon nitride layer 305 and the first oxide layer 304 to form a first contact opening 306 and expose the source/drain region 301 on the MOS device 300. Further, a first polysilicon layer 307 is deposited on the silicon nitride layer 305 and fills the first contact opening 306. The first polysilicon layer 307 is etched back until a surface of the first polysilicon layer 307 is flush with the surface of the silicon nitride layer 305 showed in FIG. 3C.
Referring to FIG. 3D, a second oxide layer 308 is formed, for example, by chemical vapor deposition (CVD) on the structure showed in FIG. 3C. The second oxide layer 308 is patterned by a photolithography step to formed a second opening 309 and to expose the contact opening 306. Then, a second polysilicon layer 310 is formed on the surface of the MOS device to cover the second oxide layer 308 and fill the second opening 309. The second polysilicon layer 310 is coupled with the first polysilicon layer 307. Further, a third oxide layer 311 is formed on the second polysilicon layer 310.
Referring to FIG. 3E, the third oxide layer 311 is etched back to expose the surface of the second polysilicon layer 310. Then, the second polysilicon layer 310 is etched back until the second oxide layer 308 is exposed.
Finally, referring to FIG. 3F, the third oxide layer 311 and the second oxide layer 308 remaining on the MOS device are removed by wet etching, in which the silicon nitride layer 305 is used as an etching stop layer. A dielectric film layer 312 is formed on the top surface of the MOS device, and a third polysilicon layer 313 is formed on the dielectric thin layer 312 to make the DRAM cylinder capacitor structure.
Cylinder capacitors are conventional capacitor structures used currently in DRAMs. The polysilicon layer is etched back to form a spacer used as a hard mask. A dummy oxide layer is dug, and a silicon nitride layer is used for a etching stop layer during the digging step. The cylinder structure increases the surface area of the capacitor to enhance the capacitance, but a disadvantage of the structure is the high stress of the silicon nitride layer. The high stress makes the cylinder structure crack in the back-ending process. Furthermore, many steps are needed to form the cylinder structure and the process is complex.